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FDS6982
June 1999
FDS6982
Dual N-Channel, Notebook Power Supply MOSFET
General Description
This part is designed to replace two single SO-8 MOSFETs in synchronous DC:DC power supplies that provide the various peripheral voltage rails required in notebook computers and other battery powered electronic devices. FDS6982 contains two unique 30V, N-channel, logic level, PowerTrenchTM MOSFETs designed to maximize power conversion efficiency. The high-side switch (Q1) is designed with specific emphasis on reducing switching losses while the low-side switch (Q2) is optimized for low conduction (less than 20m at VGS = 4.5V).
Features * *
Q2: 8.6A, 30V. RDS(on) = 0.015 @ VGS = 10V RDS(on) = 0.020 @ VGS = 4.5V Q1: 6.3A, 30V. RDS(on) = 0.028 @ VGS = 10V RDS(on) = 0.035 @ VGS = 4.5V
* * *
Fast switching speed. Low gate charge (Q1 typical = 8.5nC). High performance trench technology for extremely low RDS(ON).
Applications * Battery powered synchronous DC:DC converters. * Embedded DC:DC conversion.
D2 D2 D1 D1 G2 S2
5 6 7
Q1
4 3 2
Q2
SO-8
G1 S1
8
1
Absolute Maximum Ratings
Symbol
V DSS V GSS ID PD
T A = 25C unless otherwise noted
Parameter
Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Power Dissipation for Dual Operation Power Dissipation for Single Operation
(Note 1a) (Note 1b) (Note 1c) (Note 1a)
Q2
30 20 8.6 30 2 1.6 1 0.9 -55 to +150
Q1
30 20 6.3 20
Units
V V A W
TJ, Tstg
Operating and Storage Junction Temperature Range
C
Thermal Characteristics
RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)
78 40
C/W C/W
Package Marking and Ordering Information
Device Marking
FDS6982
(c)1999 Fairchild Semiconductor Corporation
Device
FDS6982
Reel Size
13"
Tape Width
12mm
Quantity
2500 units
FDS6982, Rev. C
FDS6982
Electrical Characteristics
Symbol Parameter
TA = 25C unless otherwise noted
Test Conditions
Type Min Typ Max Units
Off Characteristics
BVDSS BVDSS TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage, Forward VGS = 0 V, ID = 250 A ID = 250 A, Referenced to 25C VDS = 24 V, VGS = 0 V VGS = 20 V, VDS = 0 V Q2 Q1 Q2 Q1 All All All 30 30 27 26 1 100 -100 V mV/C A nA nA
Gate-Body Leakage, Reverse VGS = -20 V, VDS = 0 V
(Note 2)
On Characteristics
VGS(th) VGS(th) TJ RDS(on)
Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain-Source On-Resistance
VDS = VGS, ID = 250 A ID = 250 A, Referenced to 25C VGS = 10 V, ID = 8.6 A VGS = 10 V, ID = 8.6 A, TJ = 125C VGS = 4.5 V, ID = 7.5 A VGS = 10 V, ID = 6.3 A VGS = 10 V, ID = 6.3 A, TJ = 125C VGS = 4.5 V, ID = 5.6 A VGS = 10 V, VDS = 5 V VDS = 5 V, ID = 8.6 A VDS = 5 V, ID = 6.3 A
Q2 Q1 Q2 Q1 Q2
1 1
Q1
2.2 1.6 -5 -4 0.012 0.018 0.016 0.021 0.038 0.028
3 3
V mV/C
0.015 0.024 0.020 0.028 0.047 0.035
ID(on) gFS
On-State Drain Current Forward Transconductance
Q2 Q1 Q2 Q1
30 20 50 40
A S
Dynamic Characteristics
Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 10 V, VGS = 0 V, f = 1.0 MHz Q2 Q1 Q2 Q1 Q2 Q1 2085 760 420 160 160 70 pF pF pF
FDS6982, Rev. C
FDS6982
Electrical Characteristics
Symbol Parameter
(continued)
TA = 25C unless otherwise noted
Test Conditions
(Note 2)
Type Min
Typ
Max Units
Switching Characteristics
td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge
VDD = 15 V, ID = 1 A, VGS = 10V, RGEN = 6
Q2 VDS = 15 V, ID = 8.6 A, VGS = 5 V Q1 VDS = 15 V, ID = 6.3 A,VGS = 5 V
Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1
15 10 11 14 36 21 18 7 18.5 8.5 7.3 2.4 6.2 3.1
27 18 20 25 58 34 29 14 26 12
ns ns ns ns nC nC nC
Drain-Source Diode Characteristics and Maximum Ratings
IS VSD Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward VGS = 0 V, IS = 1.3 A Voltage VGS = 0 V, IS = 1.3 A
(Note 2) (Note 2)
Q2 Q1 Q2 Q1
0.72 0.74
1.3 1.3 1.2 1.2
A V
Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RJA is determined by the user's board design.
a) 78 C/W when mounted on a 0.5 in2 pad of 2 oz. copper.
b) 125 C/W when mounted on a 0.02 in2 pad of 2 oz. copper.
c) 135 C/W when mounted on a 0.003 in2 pad of 2 oz. copper.
Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%
FDS6982, Rev. C
FDS6982
Typical Characteristics: Q2
50 VGS = 10V 40 5.0V 4.5V
2 1.8 1.6 1.4 VGS = 4.0V
30
4.0V
4.5V 5.0V
20
1.2
6.0V 7.0V 10V
3.5V 10 3.0V 0 1 2 3 4
1 0.8 0 10 20
0
30
40
50
VDS, DRAIN-SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Drain Current and Gate Voltage.
1.6
ID = 8.6A VGS = 10V
0.04
ID = 4.5A
0.03
1.4
1.2
0.02
TA = 125 C
o
1
0.01
TA = 25 C
o
0.8
0.6 -50 -25 0 25 50 75 100
o
0
125
150
2
4
6
8
10
TJ, JUNCTION TEMPERATURE ( C)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with Temperature.
Figure 4. On-Resistance Variation with Gate-to-Source Voltage.
50 VDS = 5V 40
100
TA = -55 C
o
25 C 125 C
o
o
VGS = 0V 10 TA = 125 C 1
o
30
0.1
25 C -55 C
o
o
20
0.01 0.001 0.0001
10
0 1 2 3 4 5 6
0
0.4
0.8
1.2
1.6
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature.
FDS6982, Rev. C
FDS6982
Typical Characteristics: Q2
(continued)
10 ID = 8.6A 8 15V VDS = 5V 10V
3000 2500 CISS 2000 f = 1MHz VGS = 0 V
6 1500 4 1000 2 500 0 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30
COSS CRSS
0
Qg, GATE CHARGE (nC)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate-Charge Characteristics.
Figure 8. Capacitance Characteristics.
100 RDS(ON) LIMIT 10 100s 1ms 10ms 100ms 1s 10s DC VGS = 10V SINGLE PULSE RJA = 135 C/W TA = 25 C 0.01 0.1 1 10 100
o o
30 SINGLE PULSE 25 20 15 10 5 0 0.01 0.1 1 10 100 1000 RJA = 135 C/W TA = 25 C
o o
1
0.1
VDS, DRAIN-SOURCE VOLTAGE (V)
SINGLE PULSE TIME (SEC)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power Dissipation.
FDS6982, Rev. C
FDS6982
Typical Characteristics: Q1
40 VGS = 10V 6.0V 4.5V 4.0V
2 1.8 1.6 3.5V VGS = 3.5V 4.0V 4.5V 3.0V 1.2 1 2.5V 5.0V 6.0V 10V
30
20
1.4
10
0 0 1 2 3 4
0.8 0 10 20 ID, DRAIN CURRENT (A) 30 40
VDS, DRAIN-SOURCE VOLTAGE (V)
Figure 11. On-Region Characteristics.
Figure 12. On-Resistance Variation with Drain Current and Gate Voltage.
1.6
0.08
ID = 6.3A VGS = 10V
0.06
ID = 3.5A
1.4
1.2
0.04
TA = 125 C
o
1
0.02
0.8
TA = 25 C
o
0.6 -50 -25 0 25 50 75 100
o
0
125
150
2
4
6
8
10
TJ, JUNCTION TEMPERATURE ( C)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 13. On-Resistance Variation with Temperature.
Figure 14. On-Resistance Variation with Gate-to-Source Voltage.
40 VDS = 5V 30
100 TA = -55 C
o
25 C
o
VGS = 0V 125 C
o
10 1 TA = 125 C 25 C
o o
20
0.1 0.01
-55 C
o
10 0.001 0 1 2 3 4 5 6 0.0001 0 0.4 0.8 1.2 1.6
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 15. Transfer Characteristics.
Figure 16. Body Diode Forward Voltage Variation with Source Current and Temperature.
FDS6982, Rev. C
FDS6982
Typical Characteristics: Q1
(continued)
10 ID = 6.3A 8 15V VDS = 5V 10V
1200 1000 800 f = 1MHz VGS = 0 V
6 600 4 400 2 200 0 0 4 8 Qg, GATE CHARGE (nC) 12 16 0 5 10 15
CISS
COSS CRSS
0
20
25
30
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 17. Gate-Charge Characteristics.
Figure 18. Capacitance Characteristics.
100 RDS(ON) LIMIT 10 10ms 100ms 1s 10s DC VGS = 10V SINGLE PULSE RJA = 135 C/W TA = 25 C 0.01 0.1 1 10 100
o o
30 SINGLE PULSE 100s 1ms 25 20 15 10 5 0 0.01 0.1 1 10 100 1000 RJA = 135 C/W TA = 25 C
o o
1
0.1
VDS, DRAIN-SOURCE VOLTAGE (V)
SINGLE PULSE TIME (SEC)
Figure 19. Maximum Safe Operating Area.
Figure 20. Single Pulse Maximum Power Dissipation.
FDS6982, Rev. C
FDS6982
Typical Characteristics: Q1 & Q2
(continued)
1
r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE
0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0001
D = 0.5 0.2 0.1 0.05 0.02 0.01 Single Pulse P(pk)
R JA (t) = r(t) * R JA R JA = 135C/W
t1
t2
TJ - TA = P * R JA (t) Duty Cycle, D = t1 /t2
0.001 0.01 0.1 t 1, TIME (sec) 1 10 100 300
Figure 21. Transient Thermal Response Curve.
FDS6982, Rev. C
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging Configuration: Figure 1.0
N
ELECTROSTATIC SENSITIVE DEVICES
DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS
TNR DATE PT NUMBER PEEL STRENGTH MIN ______________ gms MAX _____________ gms
ESD Label
Antistatic Cover Tape
Conductive Embossed Carrier Tape
F63TNR Label
Customized Label
Pin 1
F852 831N
F852 831N
SOIC-8 Unit Orientation
SOIC (8lds) Packaging Information Packaging Option Packaging type Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg) Note/Comments Standard (no flow code) TNR 2,500 13" Dia 343x64x343 5,000 0.0774 0.6060 L86Z Rail/Tube 95 530x130x83 30,000 0.0774 S62Z Bag 200 76x102x127 1,000 0.0774 Bulk D84Z TNR 500 7" Dia 184x187x47 2,500 0.0774 0.1182
343mm x 342mm x 64mm Standard Intermediate box ESD Label F63TNR Label sample
LOT: CBVK741B019 FSID: FDS9953A D/C1: D9842 D/C2: QTY1: QTY2: SPEC REV: CPN: QTY: 2500 SPEC:
F852 831N
F852 831N
F63TNLabel F63TNLabel ESD Label
QARV: (F63TNR)2
SOIC(8lds) Tape Leader and Trailer Configuration: Figure 2.0
Carrier Tape Cover Tape
Trailer Tape 160mm minimum
Components
Leader Tape 390mm minimum
November 1998, Rev. A
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape Configuration: Figure 3.0
T E1
P0
D0
F K0 Wc B0 E2 W
Tc A0 P1 D1
User Direction of Feed
Dimensions are in millimeter Pkg type SOIC(8lds) (12mm)
A0
6.50 +/-0.10
B0
5.30 +/-0.10
W
12.0 +/-0.3
D0
1.55 +/-0.05
D1
1.60 +/-0.10
E1
1.75 +/-0.10
E2
10.25 min
F
5.50 +/-0.05
P1
8.0 +/-0.1
P0
4.0 +/-0.1
K0
2.1 +/-0.10
T
0.450 +/0.150
Wc
9.2 +/-0.3
Tc
0.06 +/-0.02
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum Typical component cavity center line
0.5mm maximum
B0 20 deg maximum component rotation
0.5mm maximum
Sketch A (Side or Front Sectional View)
Component Rotation
A0 Sketch B (Top View)
Typical component center line
Sketch C (Top View)
Component lateral movement
SOIC(8lds) Reel Configuration: Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A Max
Dim A max
Dim N
See detail AA
7" Diameter Option
B Min Dim C See detail AA W3
Dim D min
13" Diameter Option
W2 max Measured at Hub DETAIL AA
Dimensions are in inches and millimeters
Tape Size
12mm
Reel Option
7" Dia
Dim A
7.00 177.8 13.00 330
Dim B
0.059 1.5 0.059 1.5
Dim C
512 +0.020/-0.008 13 +0.5/-0.2 512 +0.020/-0.008 13 +0.5/-0.2
Dim D
0.795 20.2 0.795 20.2
Dim N
5.906 150 7.00 178
Dim W1
0.488 +0.078/-0.000 12.4 +2/0 0.488 +0.078/-0.000 12.4 +2/0
Dim W2
0.724 18.4 0.724 18.4
Dim W3 (LSL-USL)
0.469 - 0.606 11.9 - 15.4 0.469 - 0.606 11.9 - 15.4
12mm
13" Dia
(c) 1998 Fairchild Semiconductor Corporation
November 1998, Rev. A
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in: inches [millimeters]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM
DISCLAIMER
ISOPLANARTM MICROWIRETM POPTM PowerTrenchTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 TinyLogicTM
UHCTM VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

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